Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

how to generate a reset signal in Altera Cyclone Ⅳ series?

Verilog: input reset; reg counting; always@(posedge clk or negedge reset) begin if(!reset) counting <= 11'd0; end reset signal is connect to “M1” pin. is it counting =...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

According to your post "M1" is input, not output.

If you mean that another pin could generate falling edge at power up, No.

--- Quote End ---

I used "counting <= 11'd1" to replace "counting <= 11'd0"

after power on, Counting is actually equal to 1, I want to konw where this “reset” falling edge come from?

this reset signal is connected to FPGA's “M1” pin. is it from FPGA device?