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Honored Contributor
Honored Contributorhow to generate a reset signal in Altera Cyclone Ⅳ series?
Verilog:
input reset;
reg counting;
always@(posedge clk or negedge reset)
begin
if(!reset)
counting <= 11'd0;
end reset signal is connect to “M1” pin. is it counting =...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- but i uesd "counting <= 11'd1" to replace "counting <= 11'd0" after power on, Counting is actually equal to 1, why? --- Quote End --- You've not posted any code with the instruction "counting <= 11'd1". Why not just try using the exact code msj posted on# 2 ?
