how to generate a reset signal in Altera Cyclone Ⅳ series?

Yes, but it will not increase and remains zero permanently.

    input reset;
    reg counting;
    reg r_reset_n;
    always@(posedge clk or negedge reset)
    begin
        if(!reset)
            begin
                counting <= 11'd0;
                r_reset_n <= 1'b0;
            end
        else
            if (counting <= 11'd1234)// replace 11'd1234 with required reset delay, based on clock frequency, in order to remove glitches.
                begin
                    counting <= counting + 1'b1;
                    r_reset_n <= 1'b0;
                end
            else
                begin
                    counting <= 11'd2047;
                    r_reset_n <= 1'b1;
                end
    end