How to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA

Hi,

Could you use Synchronized Asynchronous Reset to avoid metastability issue?

You may refer to Example 57 for HDL Code for Synchronized Asynchronous Reset

https://www.intel.la/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-recommendations.pdf

Thanks.

Hello YY

Thank you for your quick answer. We already use synchronized asynchronous resets. The <arst_n> signal is generated with the following logic:

p_rst: process(pll_lock_n, s_clk)
begin
   if pll_lock_n = '0' then
      s_arst_n <= (others => '0');
   elsif rising_edge(s_clk) then
      s_arst_n <= s_arst_n(s_arst_n'high-1 downto 0) & '1';
   end if;
end process p_rst;
arst_n <= s_arst_n(s_arst_n'high);

I can describe the logic in two processes, but in my opinion this makes the code confusing.

process(arst_n, clk)
begin
   if arst_n = '0' then 
      s_valid <= '0';
   elsif rising_edge(clk) then 
      s_valid <= valid;
   end if;
end process:
 
process(clk)
begin
    if rising_edge(clk) then 
        s_data <= data; 
    end if;
end process:

Is there a way to describe the logic in one process without the disadvantage of the Global Enables?

Does s_data even need to be in a clocked process? If s_data can be anything and it's only used when s_valid is valid, could you simply do:

s_data <= data;

or some type of conditional assignment to decide when s_data should be updated?

#iwork4intel

Hi

Yes, <s_data> needs a clocked process. The given process is only a simplified example. For example, we have Avalon-Stream Pipeline modules which are very similar to the given example.

Hi,

Could you see if the below changes fit your design requirements?

process(arst_n, clk)

begin

if arst_n = '0' then -- reset case

s_valid <= '0';

elsif rising_edge(clk) then -- normal case

s_valid <= valid;

end if;

end process;

process(clk)

begin

if rising_edge(clk) then

s_data <= data; --[511:0] -- no reset

end if;

end process;

Thanks.

Hello YY

Everything is fine if I describe the logic in two processes. Than no clock enbales are synthesized.

But I was hoping somebody would have a better solution. When the logic becomes more complex (this logic is a very simple example), the description with two processes can be hard for other developers to read/understand.

Hello,

Thank for your support. I think we can mark this case as solved.