How to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA

Hello YY

Thank you for your quick answer. We already use synchronized asynchronous resets. The <arst_n> signal is generated with the following logic:

p_rst: process(pll_lock_n, s_clk)
begin
   if pll_lock_n = '0' then
      s_arst_n <= (others => '0');
   elsif rising_edge(s_clk) then
      s_arst_n <= s_arst_n(s_arst_n'high-1 downto 0) & '1';
   end if;
end process p_rst;
arst_n <= s_arst_n(s_arst_n'high);

I can describe the logic in two processes, but in my opinion this makes the code confusing.

process(arst_n, clk)
begin
   if arst_n = '0' then 
      s_valid <= '0';
   elsif rising_edge(clk) then 
      s_valid <= valid;
   end if;
end process:
 
process(clk)
begin
    if rising_edge(clk) then 
        s_data <= data; 
    end if;
end process:

Is there a way to describe the logic in one process without the disadvantage of the Global Enables?