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SSenn
New Contributor
New ContributorHow to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA
Hello, i have some trouble with the reset signal. I use VHDL to describe my logic. The target FPGA is an ARRIA 10. I have realized that the reset signal is connected as a global enable signal (ENA)...
Hi,
If you put s_data <= data; in the if-else condition, the data will be controlled by arst_n = '0'.
Thanks.
sstrell
Super Contributor
Super ContributorDoes s_data even need to be in a clocked process? If s_data can be anything and it's only used when s_valid is valid, could you simply do:
s_data <= data;
or some type of conditional assignment to decide when s_data should be updated?
#iwork4intel
