Forum Discussion
SSenn
New Contributor
New ContributorHow to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA
Hello, i have some trouble with the reset signal. I use VHDL to describe my logic. The target FPGA is an ARRIA 10. I have realized that the reset signal is connected as a global enable signal (ENA)...
Hi,
If you put s_data <= data; in the if-else condition, the data will be controlled by arst_n = '0'.
Thanks.
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
Could you see if the below changes fit your design requirements?
process(arst_n, clk)
begin
if arst_n = '0' then -- reset case
s_valid <= '0';
elsif rising_edge(clk) then -- normal case
s_valid <= valid;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
s_data <= data; --[511:0] -- no reset
end if;
end process;
Thanks.
