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SSenn
New Contributor
New ContributorHow to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA
Hello, i have some trouble with the reset signal. I use VHDL to describe my logic. The target FPGA is an ARRIA 10. I have realized that the reset signal is connected as a global enable signal (ENA)...
Hi,
If you put s_data <= data; in the if-else condition, the data will be controlled by arst_n = '0'.
Thanks.
SSennNew Contributor
New ContributorHi
Yes, <s_data> needs a clocked process. The given process is only a simplified example. For example, we have Avalon-Stream Pipeline modules which are very similar to the given example.
