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SSenn's avatar
SSenn
Icon for New Contributor rankNew Contributor
6 years ago
Solved

How to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA

Hello, i have some trouble with the reset signal. I use VHDL to describe my logic. The target FPGA is an ARRIA 10. I have realized that the reset signal is connected as a global enable signal (ENA)...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    6 years ago

    Hi,

    If you put s_data <= data; in the if-else condition, the data will be controlled by arst_n = '0'.

    Thanks.

SSenn's avatar
SSenn
Icon for New Contributor rankNew Contributor
6 years ago

Hello,

Thank for your support. I think we can mark this case as solved.

  • jorva's avatar
    jorva
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hello,

    I did some testing and Quartus Prime Standard (20.1) will allow registers without a reset to be used in processes together with registers having an asynchronous reset. However, Quartus Prime Pro (20.2) presents the issue discussed here.

    Is there any other means to support both types of registers (with/without reset) in Quartus Prime Pro?

    This would certainly render the code more coherent and avoid issues with legacy code.

    Thanks!