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SSenn's avatar
SSenn
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6 years ago
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How to describe a process with asynchronous reset in VHDL for the ARRIA 10 FPGA

Hello, i have some trouble with the reset signal. I use VHDL to describe my logic. The target FPGA is an ARRIA 10. I have realized that the reset signal is connected as a global enable signal (ENA)...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    6 years ago

    Hi,

    If you put s_data <= data; in the if-else condition, the data will be controlled by arst_n = '0'.

    Thanks.

SSenn's avatar
SSenn
Icon for New Contributor rankNew Contributor
6 years ago

Hello YY

Everything is fine if I describe the logic in two processes. Than no clock enbales are synthesized.

But I was hoping somebody would have a better solution. When the logic becomes more complex (this logic is a very simple example), the description with two processes can be hard for other developers to read/understand.