How to constrain the GPIO IP core of a Stratix 10 device

I'm using the Stratix 10 for DDR data acquisition. This part of the function is migrated from CycloneV, and the correctness of data acquisition is verified in cycloneV. But when I used Stratix 10's GPIO ip check ATLDDIO_IN ip core for replacement, there was a timing violation during the compilation of the project. The main problems occur in the following two areas:

1. The setup timing violation in the pin to DDIO. The reason this part appears is that since Quartus sets the input delay chain to a maximum of 63. Therefore, there is a negative margin in the setup slack, but there is a large positive margin in the hold slack. After I manually set the input delay chain to a smaller value, the pin-to-DDIO setup timing violation disappeared.

2. The setup timing violation of full-rate DDIO to the core register. When I checked the data path, I found that the full-rate DDIO output was driven by the falling edge of the clock, but the core registers are driven using the rising edge of the clock, so the relationship of the clock became smaller, resulting in a settling time violation. Instead of using any PLL to phase shift the clock, I used the same clock to drive the DDIO registers and core registers.

For question 2, how should I constrain the clock to accommodate the timing between the full-rate DDIO driven by the falling edge and the core registers driven by the rising edge.

Thank you very much for your answer.