Forum Discussion
china_cn
New Contributor
New ContributorHow to constrain the GPIO IP core of a Stratix 10 device
I'm using the Stratix 10 for DDR data acquisition. This part of the function is migrated from CycloneV, and the correctness of data acquisition is verified in cycloneV. But when I used Stratix 10's G...
Thanks for sharing. Seems like the inverter is needed so that the output data can be captured on clock falling edge in order to form full cycle latch for larger setup requirement.
china_cnNew Contributor
New ContributorThank you very much for your reply.
In fact, there is no violation of DDIO's timing. The main thing is that the path from DDIO to the core register has a timing violation.
But I saw a solution in the AN911, which is that the core registers are also latch with the falling edge of the clock. This helped my design a lot and I've successfully solved the issue.
Thanks again for your reply.
ShengN_altera
Super Contributor
Super ContributorThanks for sharing. Seems like the inverter is needed so that the output data can be captured on clock falling edge in order to form full cycle latch for larger setup requirement.
