Forum Discussion
New ContributorHow to constrain the GPIO IP core of a Stratix 10 device
Thanks for sharing. Seems like the inverter is needed so that the output data can be captured on clock falling edge in order to form full cycle latch for larger setup requirement.
Super ContributorHi,
Check the link below Full-Rate or Half-Rate DDIO Input Register .sdc Command Examples:
Image:
Probably can help you out.
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
china_cnThank you very much for your reply.
In fact, there is no violation of DDIO's timing. The main thing is that the path from DDIO to the core register has a timing violation.
But I saw a solution in the AN911, which is that the core registers are also latch with the falling edge of the clock. This helped my design a lot and I've successfully solved the issue.
Thanks again for your reply.
- ShengN_altera
Thanks for sharing. Seems like the inverter is needed so that the output data can be captured on clock falling edge in order to form full cycle latch for larger setup requirement.
