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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to activate the built-in clock inverter in LE?

Hi All,

I'm using Cyclone EP1C6.

The clock is supplied via pin152 (CLK3).

For some purpose, I use the falling edge as active edge.

This clock also connects to an on-chip memory block.

After I compile the design, I get the following critical warning.

"Critical Warning: (High) Rule C102: Logic cell should not be used to generate inverted clock. Found 1 node(s) related to this rule."

And it tells me to "Use a register clock's programmable invert to implement an inverter in the design."

I just can't find how to use the programmable inverter.

Can somebody help me?

Thank you!

Aaron

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Usually with a simple clock inversion in the source file, synthesis will figure out that it can use the clock inverter available in the LAB, DSP block (for other device families), or RAM block, which is where you want the inversion to be done.

    If you have a "keep" synthesis attribute on the inverted clock, an LCELL primitive after the inverter, or something like that, synthesis will have to invert the clock in a LUT, creating clock skew that you need to avoid.

    I didn't test this, but it might be that your warning can be given for a case with additional logic in the clock path in addition to the inversion. In that case the real problem is the other logic.

    If you are using incremental compilation design partitions, the inversion will be in a LUT if the inversion is in a design partition that does not contain the register being clocked. The inversion in the source code needs to be in the same design partition with the registers using the falling edge of the clock. There is probably a suggestion for how to handle this case in Application Note 470, "Best Practices for Incremental Compilation Partitions and Floorplan Assignments".
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    How are you describing your registers? If you use always@(negedge clk) [Verilog] or if(falling_edge(clk)) [VHDL], the resulting registers inferred by synthesis will always use the programmable invert. You only get into trouble when you manually invert the clock, in which case you'll run into trouble (as Brad points out) if there's a keep on the inverted clock signal, or you've put a partition boundary between the register and the inverter.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Brad & HDL Guru,

    Thank you for your kind relply!

    There is no additional logic in the clock path.

    I didn't invert the clock manually by any inverter, but simply use always@(negedge clk).

    There is a "keep" attribute on the clock net. After I remove the attribute and recompile the design, the critical warning disappears. And I see the inverter has been moved into LE.

    Thank you for your help! :-)

    Aaron