How to activate the built-in clock inverter in LE?

How are you describing your registers? If you use always@(negedge clk) [Verilog] or if(falling_edge(clk)) [VHDL], the resulting registers inferred by synthesis will always use the programmable invert. You only get into trouble when you manually invert the clock, in which case you'll run into trouble (as Brad points out) if there's a keep on the inverted clock signal, or you've put a partition boundary between the register and the inverter.