How to activate the built-in clock inverter in LE?

Usually with a simple clock inversion in the source file, synthesis will figure out that it can use the clock inverter available in the LAB, DSP block (for other device families), or RAM block, which is where you want the inversion to be done.

If you have a "keep" synthesis attribute on the inverted clock, an LCELL primitive after the inverter, or something like that, synthesis will have to invert the clock in a LUT, creating clock skew that you need to avoid.

I didn't test this, but it might be that your warning can be given for a case with additional logic in the clock path in addition to the inversion. In that case the real problem is the other logic.

If you are using incremental compilation design partitions, the inversion will be in a LUT if the inversion is in a design partition that does not contain the register being clocked. The inversion in the source code needs to be in the same design partition with the registers using the falling edge of the clock. There is probably a suggestion for how to handle this case in Application Note 470, "Best Practices for Incremental Compilation Partitions and Floorplan Assignments".