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Altera_Forum's avatar
Altera_Forum
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11 years ago

How generate signal DCLK?

Hi,

When the FPGA is power on and the FPGA does not have any internal configuration.

Is generated automatic the signal DCLK, to load a configuration from an EPCS?

Must I generate it with an external clock?

Regards

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Review the device handbook about AS (active serial) configuration scheme and the meaning of each involved signal. No external signals are required,

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    First thank you,

    I was reading enough and I do not have clearly. If when the fpga is "empty", without programming.

    Is this signal generated automatic? Or has it to have algun micro embedded for example nios for generate de signal?

    All that is because I want to load the program on the fpga from an epcs. And make power on from this epcs.

    Always that I it wants. Without connecting again to the PC. Is it possible this?

    https://www.alteraforum.com/forum/attachment.php?attachmentid=8653
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    All signals and interconnections are required as shown in the wiring diagram you attached. All these signals are generated automaitc by the FPGA and EPCS, thus there is no external device required for configuration.