Honored ContributorHi,
How can we see the actual placement and routing and/or where our design elements are placed on the FPGA using QuartusII ? I have synthesised a design on CycloneIII and want to see where the design elements are placed on the FPGA chip. Kindly let me know if anyone knows about this. Thanks
Honored ContributorI think you are looking for (Tools->Chip Planner) from within Quartus.
Honored ContributorHello Ted,
Thanks for your reply. In the documentation of the Chip planner says we have to adjust the "Layout Settings" to view the resources. But I am unable to view the details of the logic and routing because It says - "disabled due to automatic layer disabling at the current zoom level" . [I have attached the screen shot of it] I tried changing the Layer settings to basic, detailed etc. But no luck. Can you kindly suggest me what I need to do to zoom in to see these details?Honored ContributorI think you just need to go (View->Zoom In) repeatedly in order to get a smaller region on the display.
Honored ContributorThank you so much for the reply Ted :)
I have one more concern. In design I have attached all the M9K blocks are placed very far away from the rest of the logic. In fact the rest of the logic is all concentrated towards the edges. This will create long combinational paths which I do not want. How do we disable placement the of I/O registers into the device pin registers? What settings do we need to change? Kindly reply if anybody has an idea about this.Honored ContributorI don't have any idea what could cause that bad placement. Is it something like you've been experimenting with TimeQuest constraints / LogicLock / or fitter options? Your project is so small I feel like you ought to be quickly able to figure out what is going wrong by going back to a bare-bones (default) project with just your HDL, and then gradually add in all of your non-HDL changes (.qsf, .sdc) until you observe the placement turn out this badly.
Honored ContributorMaybe the fitter lays them out like that to being with, finds it is good enough to meet the specified timing, and stops.
