How do we see the placement & routing on the FPGA chip

Thank you so much for the reply Ted :)

I have one more concern. In design I have attached all the M9K blocks are placed very far away from the rest of the logic. In fact the rest of the logic is all concentrated towards the edges. This will create long combinational paths which I do not want.

How do we disable placement the of I/O registers into the device pin registers? What settings do we need to change? Kindly reply if anybody has an idea about this.