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Altera_Forum
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12 years ago

How do we see the placement & routing on the FPGA chip

Hi, How can we see the actual placement and routing and/or where our design elements are placed on the FPGA using QuartusII ? I have synthesised a design on CycloneIII and want to see where the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I don't have any idea what could cause that bad placement. Is it something like you've been experimenting with TimeQuest constraints / LogicLock / or fitter options? Your project is so small I feel like you ought to be quickly able to figure out what is going wrong by going back to a bare-bones (default) project with just your HDL, and then gradually add in all of your non-HDL changes (.qsf, .sdc) until you observe the placement turn out this badly.