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Altera_Forum's avatar
Altera_Forum
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12 years ago

hold slack violation

hi,

i am using a clock period of 20ns(50Mhz) , in timing analysis constraints i set input delay max=10ns,min =5ns for input port, and set output delay max=5ns,min =2ns for output port. in verifying the timing analysis setup slack is positive but the hold slack is negative (-0.327) , i tried with different max and min values for both input and output port then also hold slack is always negative with same value(-0.327).

how to remove the hold slack violation

what the procedure or any settings should i need to follow

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    There's not enough info in the screenshot. Run report_timing with -detail full_path, and add "-file ./TQ/TQ_failing_hold.txt". Then add the .txt file. (Analyzying the setup might be useful too.)

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    hi,

    i tried with different max and min values for both input and output port then also hold slack is always negative with same value(-0.327).

    how to remove the hold slack violation

    --- Quote End ---

    It sounds like you are talking about io timing problem. It is not matter of you trying some lucky numbers for delay to make TimeQuest happy with no red line failures. The principle is that you are supposed to enter your actual system figures and see if it passes. If it does not then you may rotate the clock through PLL.

    Alternatively you change your system delay figures if that is at all possible e.g. if input comes from another FPGA that you can control.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Kaz, I agree(although there are other solutions besides shifting the PLL), but something seems fishy. A set_input_delay -min of 5 should add 5ns of delay to the path. I can't imagine there being a hold violation on those inputs unless there was just a ton of clock skew, and the snapshot didn't seem to show it. I think something is up with the constraints. (Also, the fact that changing the constraints and they get the same hold slack doesn't make any sense at all.)