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Altera_Forum
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13 years ago

hold slack violation

hi, i am using a clock period of 20ns(50Mhz) , in timing analysis constraints i set input delay max=10ns,min =5ns for input port, and set output delay max=5ns,min =2ns for output port. in ve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Kaz, I agree(although there are other solutions besides shifting the PLL), but something seems fishy. A set_input_delay -min of 5 should add 5ns of delay to the path. I can't imagine there being a hold violation on those inputs unless there was just a ton of clock skew, and the snapshot didn't seem to show it. I think something is up with the constraints. (Also, the fact that changing the constraints and they get the same hold slack doesn't make any sense at all.)