Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

hold slack violation

hi, i am using a clock period of 20ns(50Mhz) , in timing analysis constraints i set input delay max=10ns,min =5ns for input port, and set output delay max=5ns,min =2ns for output port. in ve...