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Honored Contributor
Honored Contributorhold slack violation
hi, i am using a clock period of 20ns(50Mhz) , in timing analysis constraints i set input delay max=10ns,min =5ns for input port, and set output delay max=5ns,min =2ns for output port. in ve...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- hi, i tried with different max and min values for both input and output port then also hold slack is always negative with same value(-0.327). how to remove the hold slack violation --- Quote End --- It sounds like you are talking about io timing problem. It is not matter of you trying some lucky numbers for delay to make TimeQuest happy with no red line failures. The principle is that you are supposed to enter your actual system figures and see if it passes. If it does not then you may rotate the clock through PLL. Alternatively you change your system delay figures if that is at all possible e.g. if input comes from another FPGA that you can control.
