Forum Discussion
Honored Contributorhigh speed pulse generation
I have an application in which I will be using a NIOS with some low speed logic ~30Mhz or so, but I also need to have a small part of my logic for generating high speed, high resolution pulse trains on the order of 1ns resolution. What is the feasibility of doing both tasks in the same device? Does Altera have anything suitable for the high speed requirement or should I be looking at a programmable timer chip?
11 Replies
Altera_ForumIt sounds most like the timing generator in ATE. I had ever designed the digital channel board in a ATE. FPGA is not a good candidate.
- Altera_Forum
Yes, delay lines like this are a sure solution and the way I am leaning. There is more complexity and they aren't cheap either. There are also temperature dependencies which would be easier to control inside one device.
- Altera_Forum
What about these ones ?
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2608 - Altera_Forum
This is one way I was thinking it could work, but I didn't know about the x10 mode. I would need a larger buffer than 10bits, but at least that only needs to work at 100Mhz. I have a different solution now using delay lines but I will keep this in mind. What do you think is the cheapest/lowest grade family that would be capable of this?
- Altera_Forum
The 1ns resolution should be achievable using ALT_LVDS transmitter running at 1GHz. You can set LVDS TX at x 10 mode and have the parallel clock run at 100MHz. This translates to 10 parallel bits each for channel A and B. You can then use Nios to update these 20 bits with the pulse pattern and offset. Without any additional logic, the update time will be limited by the frequency Nios is running at. If you can add additional logic or SM running at 100MHz, you should be able to repeatedly generate the pulse and timing you want.
- Altera_Forum
Search www.altera.com for "altpll_reconfig" to get to the altpll_reconfig megafunction user guide, application notes for use with specific device families, design examples, etc.
- Altera_Forum
My experience with the altera PLLs is that they are intended to be tuned once for your design and left at that setting. If I could also perform dynamic adjustments that might be ideal , but I have not seen anything that would suggest it is possible. If you know of any app note or example, please let me know. I believe some of the xilinx parts incorporate DLLs which may be even more applicable provided you can get at those registers after configuration.
- Altera_Forum
I do not think you will be able to accomplish what you want using the High Speed Serial transceivers in the GX families.
In your restatement of desired situation, what you are really looking for is fine grained starting edge capability of the pule trains. (from one to the other) You might be able to do this with PLL dynamic phase controls. I would look into that potential. - Altera_Forum
I will need LVDS to TTL buffers, but that is no problem. I am more concerned that there is some flaw in my scheme. I can read those cyclone or stratix data sheets for hours and still not come away with any certainty. After some thought, I realize my description of what I need is misleading. The basic requirement is to xmit a pulse on both chA and chB, with programatic control of the delay between them. The duration of the pulses is not critical, but the delay between channels must be accurate to 1ns in a range from 0 to 250ns. If there is a better way to this than what I have described, let me know.
- Altera_Forum
Check that the I/O standard(s) (LVDS and perhaps something similar) that can be used with the serial transceivers in your device are suitable for your application.
