Hi ​I would like to ask a questions about measure BSC package outline dimension.

Hi,

Thank you for contacting Intel Community.

Please allow me some time to check this with our internal team. Appreciate much on your patience. Thank you.

Regards,

Aim

Hi,

We apologize for the delay in response as we are still investigate this matter. In the mean time, kindly provide the target device OPN for us to investigate more into this.

Thank you.

Hi,

Part number EP1C3T100C6N package https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/pkgds.pdf#page=67-68

This question about how to conform specification for all Intel FPGA package with BSC dimension, if BSC dimension do not have tolerance? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/pkgds.pdf

Hi Andrey,

I just got this from internal team. BSC does not have tolerance. All our POD is following JEDEC specification. For this OPN, we follow JEDEC spec, MS-026- D variance AED. Intel's representative has sent you some information through private message. Please take a look.

Regards,

Aim

Hi,

We are very sorry that we can't help that much but by following JEDEC standard, BSC has no tolerance.

According to our KDB, BSC means basic spacing between centers which has no tolerance. Apologize for the inconveniences.

KDB: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07152011_585.html

Regards,

Aim