Help on understanding HDL module "always" clock transitions

• clk - 10ns/50%
• baudSelector - whith whatever value from 3'b000 - 3'b111

The attached simulation of two cases demonstrates.

module counter(clk, out , count, baudSelector , clkSTB, srst, xcount2 );

  input [2:0] baudSelector;
  input srst;
  input clk;
  output reg out;
  output reg[7:0] count;
  output reg[14:0] xcount2;
  output reg clkSTB;

  initial begin
     count = 0;
	  xcount2 = 0;
	  clkSTB = 0;
	  out = 0;
  end

  always @(posedge clk) begin 
  	if( xcount2[10:0] == 11'd433 ) 
	begin
		count <= count + 1; 
	end
	out <= count[4];
  end	
  
  always @(posedge clk) begin 
  	if( srst ) 
	begin
		{ clkSTB , xcount2 } <= 16'd0;
	end

	//  --  115200 ;; 50000000/115200 -> 434
	//  --  57600 ;; 50000000/57600 -> 868
	//  --  38400 ;; 50000000/38400 -> 1302
	//  --  19200 ;; 50000000/19200 -> 2604
	//  --  INVALIDOS :: default 9600 ;; 50000000/9600 -> 5208
	//
	//  3'b000 : { clkSTB, xcount2 } <= xcount2 + 16'd434 ;
	//  3'b001 : { clkSTB, xcount2 } <= xcount2 + 16'd868 ;
	//  3'b010 : { clkSTB, xcount2 } <= xcount2 + 16'd1302 ;
	//  3'b011 : { clkSTB, xcount2 } <= xcount2 + 16'd2604 ;
	//  default: { clkSTB, xcount2 } <= xcount2 + 16'd5208 ;
	//	
	case(baudSelector)
	  3'b000 : begin
			if( xcount2 >= 15'd434 ) 
			begin
				clkSTB <= 1;
				xcount2 <= 0;
			end
			else
			begin
				clkSTB <= 0;
				xcount2 <= xcount2 + 1;
			end				
	  end	// { clkSTB, xcount2 } <= xcount2 + 16'd434 ;
	  3'b001 :
	 			if( xcount2 >= 15'd868 ) 
			begin
				clkSTB <= 1;
				xcount2 <= 0;
			end
			else
			begin
				clkSTB <= 0;
				xcount2 <= xcount2 + 1;
			end
	  3'b010 : 
			if( xcount2 >= 15'd1302 ) 
			begin
				clkSTB <= 1;
				xcount2 <= 0;
			end
			else
			begin
				clkSTB <= 0;
				xcount2 <= xcount2 + 1;
			end
	  3'b011 : 
  			if( xcount2 >= 15'd2604 ) 
			begin
				clkSTB <= 1;
				xcount2 <= 0;
			end
			else
			begin
				clkSTB <= 0;
				xcount2 <= xcount2 + 1;
			end
	  default: 
  			if( xcount2 >= 15'd5208 ) 
			begin
				clkSTB <= 1;
				xcount2 <= 0;
			end
			else
			begin
				clkSTB <= 0;
				xcount2 <= xcount2 + 1;
			end
	endcase
	
  end
  
endmodule