FredcwGO_BR
New Contributor
New ContributorHelp on understanding HDL module "always" clock transitions
Howdy all,
I'm a newbee on FPGA, and needing to use QuartusII 13.0.1 for this is the EPM7128 board that i have.
The following code compiles but simulation does not show what i expected.
In the simulation for 50uS , feeding
- clk - 10ns/50%
- baudSelector - whith whatever value from 3'b000 - 3'b111
The attached simulation of two cases demonstrates.
Out signal (which drives de board led) is the one i'm interested on; it should be the same frequency for whatever baudSelector input.
I expected that the "if xcount2[] == " (line 19) guard condition, would only fire
at every time the xcount2 counter goes thru it at that count, but it looks that fires along with the clkSTB.
Can't figure what i'm doing wrong.
Quartus II Web Edition 13.0.1 / 13.1sp1
Debian (bookworm) Linux 64bit
Target devices: EPM7128 / EPM240T100
module counter(clk, out , count, baudSelector , clkSTB, srst, xcount2 ); input [2:0] baudSelector; input srst; input clk; output reg out; output reg[7:0] count; output reg[14:0] xcount2; output reg clkSTB; initial begin count = 0; xcount2 = 0; clkSTB = 0; out = 0; end always @(posedge clk) begin if( xcount2[10:0] == 11'd433 ) begin count <= count + 1; end out <= count[4]; end always @(posedge clk) begin if( srst ) begin { clkSTB , xcount2 } <= 16'd0; end // -- 115200 ;; 50000000/115200 -> 434 // -- 57600 ;; 50000000/57600 -> 868 // -- 38400 ;; 50000000/38400 -> 1302 // -- 19200 ;; 50000000/19200 -> 2604 // -- INVALIDOS :: default 9600 ;; 50000000/9600 -> 5208 // // 3'b000 : { clkSTB, xcount2 } <= xcount2 + 16'd434 ; // 3'b001 : { clkSTB, xcount2 } <= xcount2 + 16'd868 ; // 3'b010 : { clkSTB, xcount2 } <= xcount2 + 16'd1302 ; // 3'b011 : { clkSTB, xcount2 } <= xcount2 + 16'd2604 ; // default: { clkSTB, xcount2 } <= xcount2 + 16'd5208 ; // case(baudSelector) 3'b000 : begin if( xcount2 >= 15'd434 ) begin clkSTB <= 1; xcount2 <= 0; end else begin clkSTB <= 0; xcount2 <= xcount2 + 1; end end // { clkSTB, xcount2 } <= xcount2 + 16'd434 ; 3'b001 : if( xcount2 >= 15'd868 ) begin clkSTB <= 1; xcount2 <= 0; end else begin clkSTB <= 0; xcount2 <= xcount2 + 1; end 3'b010 : if( xcount2 >= 15'd1302 ) begin clkSTB <= 1; xcount2 <= 0; end else begin clkSTB <= 0; xcount2 <= xcount2 + 1; end 3'b011 : if( xcount2 >= 15'd2604 ) begin clkSTB <= 1; xcount2 <= 0; end else begin clkSTB <= 0; xcount2 <= xcount2 + 1; end default: if( xcount2 >= 15'd5208 ) begin clkSTB <= 1; xcount2 <= 0; end else begin clkSTB <= 0; xcount2 <= xcount2 + 1; end endcase end endmodule
Hi,
it's the design concept.
The condition if( xcount2[10:0] == 11'd433 ) can't produce constant frequency, evenly spaced events when applied to the 15 bit baud rate counter.
You can however easily achieve waht you want by slightly rearrangind the design:1. have a 115k2 tic counter producing you constant frequency tic.
2. divide the 115k2 tic down according to select baud rate, fortunately they involve integer frequency ratios.
Your time constants are 1 clock period off, by the way.
