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FredcwGO_BR
New Contributor
New ContributorHelp on understanding HDL module "always" clock transitions
Howdy all, I'm a newbee on FPGA, and needing to use QuartusII 13.0.1 for this is the EPM7128 board that i have. The following code compiles but simulation does not show what i expected. In...
Hi,
it's the design concept.
The condition if( xcount2[10:0] == 11'd433 ) can't produce constant frequency, evenly spaced events when applied to the 15 bit baud rate counter.
You can however easily achieve waht you want by slightly rearrangind the design:1. have a 115k2 tic counter producing you constant frequency tic.
2. divide the 115k2 tic down according to select baud rate, fortunately they involve integer frequency ratios.
Your time constants are 1 clock period off, by the way.
sstrell
Super Contributor
Super ContributorWhat you're looking for isn't super clear, but it sounds like the "out" assignment is supposed to be between begin/end because otherwise, out is just count[4] every clock cycle. And if you do that, you should have a concluding else clause:
always @(posedge clk) begin if( xcount2[10:0] == 11'd433 ) begin count <= count + 1; out <= count[4]; end else... end
