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Altera_Forum
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Honored Contributorhelp ON EP2S60 FPGA
The FPGA refuse to work after I program it! I use two way to program my design, one is programming to EPC16 which is connect to FPGA, another is
programming to FPGA directly. but FPGA has no reaction after programming,although the process is going on sucessfuly to 100%. this problem comes suddenly, as this FPGA work correctly before.any one who once met this problem ,give me help ,thanks!13 Replies
Altera_Forum--- Quote Start --- Yes I allready did that, it's a Mezzanine board normally tested in a system. But also possible to test it seperately. It's not only the TDO but I think the complete TAP is disappeared after erase with quartus. I tried to put the device in extest but nothing happened. The only thing I can think of is that the erase action is writing something in the private registers ( see the last lines from the ep2s60 bsdl) : "The following private instructions must not be used as they"& "may render the device inoperable:"& " "& " 1100010000 "& " 0011001001 "& " 0000101001 "& " 0000010000 "& " "& "Customer should take precautions not to invoke these instructions"& "at any time. Contact Altera Applications for further assistance."; --- Quote End --- Hi, sorry I'm not a JTAG expert. Maybe you should contact the altera Application guy's. Kind regards GPK- Altera_Forum
Yes I allready did that, it's a Mezzanine board normally tested in a system.
But also possible to test it seperately. It's not only the TDO but I think the complete TAP is disappeared after erase with quartus. I tried to put the device in extest but nothing happened. The only thing I can think of is that the erase action is writing something in the private registers ( see the last lines from the ep2s60 bsdl) : "The following private instructions must not be used as they"& "may render the device inoperable:"& " "& " 1100010000 "& " 0011001001 "& " 0000101001 "& " 0000010000 "& " "& "Customer should take precautions not to invoke these instructions"& "at any time. Contact Altera Applications for further assistance."; - Altera_Forum--- Quote Start --- I am using the USB byte blaster rev B. Before I do a Erase action the Quartus (9.0) and do auto detect the chain is seen correct. Both with the USB blaster and the Jtag Technologies hard/software. Now starts the problem : after I do a "erase" with quartus and do a power dwn up again there's no chain seen with both tools (JT and USB blaster). The TDO is only high ( it looks like high Z). Hans --- Quote End --- Hi Hans, is it possible for you to change the JTAG Chain, so that only your Stratix Devcie is in the Chain ? Kind regards GPK
- Altera_Forum
I am using the USB byte blaster rev B.
Before I do a Erase action the Quartus (9.0) and do auto detect the chain is seen correct. Both with the USB blaster and the Jtag Technologies hard/software. Now starts the problem : after I do a "erase" with quartus and do a power dwn up again there's no chain seen with both tools (JT and USB blaster). The TDO is only high ( it looks like high Z). Hans - Altera_Forum--- Quote Start --- I did not noticed If programming was successful, I found out after programming that the device did not configure ( via epcs64 and quartus 9.0). But my problem is now that the normal boundary scan test passed before programming the device , did some ddr ram test with boundary sacn ,all ok. Then I came to the conclusion that I was using the wrong programming file and used Quartus 9.0 to erase the epcs64 . After this erase : I can not use the EP2S60 anymore, not with the USB blaster , not with the standard boaundary scan tools . I looks like the TAP controller is not working any more. I thought it was board dependend but when I tried this on the second board with a EP2S60 : the same problem after the erase . TAP is not working !! Am I the first with this problem ? Tnx Hans --- Quote End --- Hi, what kind of programming HW do you use (USB-Blaster?) ? What happend when you choose "Auto detect" in the programmer ? What HW is selected ? Kind regards GPK
- Altera_Forum
I did not noticed If programming was successful, I found out after programming that the device did not configure ( via epcs64 and quartus 9.0).
But my problem is now that the normal boundary scan test passed before programming the device , did some ddr ram test with boundary sacn ,all ok. Then I came to the conclusion that I was using the wrong programming file and used Quartus 9.0 to erase the epcs64 . After this erase : I can not use the EP2S60 anymore, not with the USB blaster , not with the standard boaundary scan tools . I looks like the TAP controller is not working any more. I thought it was board dependend but when I tried this on the second board with a EP2S60 : the same problem after the erase . TAP is not working !! Am I the first with this problem ? Tnx Hans - Altera_Forum--- Quote Start --- Maybe it has nothing to do with this problem. I am having a EP2S60 but the configuration file was compiled for a EP2S130. Programmed the device with the wrong file. Tried to erase ( with the byte blaster) but I can not get connect to the device anymore. Also with Boundary scan tools (Jtag Techn) there's no reponse (TDO is continue 1) rgrd's Hans --- Quote End --- Hi Hans, you tried to programm a EP2S60 with a file for an EP2S130 ????:confused: I don't think that the programmer will finish successful. Kind regards GPK
- Altera_Forum--- Quote Start --- The FPGA refuse to work after I program it! I use two way to program my design, one is programming to EPC16 which is connect to FPGA, another is programming to FPGA directly. but FPGA has no reaction after programming,although the process is going on sucessfuly to 100%. this problem comes suddenly, as this FPGA work correctly before.any one who once met this problem ,give me help ,thanks! --- Quote End --- Maybe it has nothing to do with this problem. I am having a EP2S60 but the configuration file was compiled for a EP2S130. Programmed the device with the wrong file. Tried to erase ( with the byte blaster) but I can not get connect to the device anymore. Also with Boundary scan tools (Jtag Techn) there's no reponse (TDO is continue 1) rgrd's Hans
- Altera_Forum
development kit or your board?
- Altera_Forum--- Quote Start --- Have you tried measuring the clocks, pll lock signals and resets? Another thing can be to program something else into the fpga. Some simple design that toggles pins or something like that just to see if the FPGA or the design is the problem. Best Regards, Ola Bångdahl (trying to avoid doing actual work...) --- Quote End --- Thank you for your reply. May be ,I see. I'm try to check whether the crystalloid is OK.
