Help Needed: Implementing UART and SPI on Altera MAX II EPM240 CPLD

Hi,

For SPI master, you may check this design example https://www.intel.com/content/www/us/en/docs/programmable/683277/current/serial-peripheral-interface-master-in.html

This application note details the implementation of the SPI master in MAX II, MAX V and MAX 10 devices.

Design link: https://www.intel.com/content/www/us/en/design-example/715016/intel-max-10-fpga-an-485-serial-peripheral-interface-master-design-example.html

Will provide the UART part later.

Thanks,

Regards,

Sheng

Hi,

The link provided for SPI master on max 10 is SPI master verilog code with no pin assignments which can be implemented on max ii as well check the document note. As for the pin assignment you need to assign based on the max ii pins. We don't have design straight for max ii.

Thanks,

Regards,

Sheng

Hi,

Forgot to mention that you need to open the design file AN485_MAX10.par with Quartus version 18.0std then will see the verilog code

Hi,

For the uart, we have only uart ip but don't have verilog code design example.

I think you can choose an open source uart verilog code to start with.

For example, I had tested the uart verilog code from this link https://github.com/ben-marshall/uart/tree/master with our uart design example link https://www.intel.com/content/www/us/en/design-example/715139/cyclone-v-fpga-uart-rs-232-maximum-baud-rate-reference-design.html

I had used MAX 10 and replaced the second uart uart_1 with the open source uart verilog code and it works well. Based on the CV_SOC_UART_project\software\software\UART_RXTX\main.c, I had sent data 100, 25, 5, 6 from uart_0 to open source uart verilog code. Open source uart received correctly. Check attached file and screenshot.

I don't have MAX II with me but I think open source uart verilog code should work in MAX II as well.

Thanks,

Regards,

Sheng

Hi

Yes, you can implement UART, SPI, and I2C protocols directly in the MAX II CPLD using Verilog or VHDL. The CPLD is well-suited for custom digital logic, including serial communication interfaces.

UART: Implement a UART TX/RX module. Connect the CPLD’s tx and rx pins to the microcontroller’s UART pins.

SPI: Implement SPI master or slave logic in the CPLD. Connect MOSI, MISO, SCLK, and SS pins between the CPLD and microcontroller.

I2C: Implement I2C master or slave logic. Connect SDA and SCL lines.

You can implement those protocols in the MAX II CPLD using HDL. Connect the CPLD’s I/O pins/gpio pins to the microcontroller’s corresponding pins, ensuring voltage compatibility.

Hi,

I'm using one of the embedded design to show that the open source uart verilog code is working.

To use uart in MAX II, you can just straight use the uart verilog code in your design. And assign appropriate clock and gpio/IO pins to the clk, tx, rx.

Thanks,

Regards,

Sheng

Hi,

Forgot to mention that you need to change device under Device tab.

Hi,

Since I use the embedded peripherals on MAX 10 to showcase, MAX II not support some of the embedded peripherals so you may remove those peripherals and just use the UART verilog code.

Change device is under Device tab not Board tab.

Thanks,

Regards,

Sheng

Hi,

Yes, MAX II don't support some of the embedded peripheral. However you just need the UART verilog code. You can create a new MAX II project and include these 3 files impl_top.v, uart_rx.v and uart_tx.v from this link https://github.com/ben-marshall/uart/tree/master/rtl (I had verify the functionality)

If you want to run that design, you'll need to change to device MAX 10 with name 10M50DAF484C6GES

Thanks,

Regards,

Sheng

Hi,

May I know do you have any further concern or consideration?

Thanks,

Regards,

Sheng