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Thiru_N's avatar
Thiru_N
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5 months ago

Help Needed: Implementing UART and SPI on Altera MAX II EPM240 CPLD

Hi everyone, I'm currently working with the Altera MAX II EPM240T100C5N CPLD and I'm trying to implement UART and SPI communication protocols on it. I'm using Verilog HDL and targeting a 3.3V logic ...
Programmable Logic Device
ShengN_altera's avatar
ShengN_altera
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5 months ago

Hi,

For the uart, we have only uart ip but don't have verilog code design example.

I think you can choose an open source uart verilog code to start with.

For example, I had tested the uart verilog code from this link https://github.com/ben-marshall/uart/tree/master with our uart design example link https://www.intel.com/content/www/us/en/design-example/715139/cyclone-v-fpga-uart-rs-232-maximum-baud-rate-reference-design.html

I had used MAX 10 and replaced the second uart uart_1 with the open source uart verilog code and it works well. Based on the CV_SOC_UART_project\software\software\UART_RXTX\main.c, I had sent data 100, 25, 5, 6 from uart_0 to open source uart verilog code. Open source uart received correctly. Check attached file and screenshot.

I don't have MAX II with me but I think open source uart verilog code should work in MAX II as well.

Thanks,

Regards,

Sheng