Help: Cyclone 10CL025YE144 implementing LVDS receiver and what pins I can do this on and how>

Dear All,

I hope this message finds you well. I am currently exploring the implementation of LVDS directly on an FPGA, particularly on a Cyclone 10 LP device. My aim is to interface it with an LVDS device that outputs a simple 1 pulse per second signal. It's worth noting that I don't require SERDES functionality for this task, as the 1 pulse per second data is not encoded – it can be viewed as 'normal' on/off binary.

To initiate this integration within Quartus, I began by creating a basic schematic in my top-level design file. I simply placed an input pin and an output pin, connecting them together to create a straightforward test device. Upon compilation, the process was successful without any issues.

Moving on to the pin-planner, I located the input pin and adjusted its IO standard to LVDS. As expected, the pin-planner automatically generated 1pps(n), considering the requirement for two pins in LVDS. However, I encountered a surprising limitation at this stage. Despite the flexibility expected, I found that I could only choose from around 10 possible pin locations. This left me somewhat perplexed, as it appears that only a select few of the I/O pins on the 10CL025 are useable as LVDS receivers. This seems somewhat restrictive to me.

I would greatly appreciate any insights or guidance on this matter. Am I overlooking something fundamental, or perhaps approaching this process incorrectly?

Additionally, if anyone could direct me to a beginner's guide or instructional video on the utilization of LVDS in the Cyclone 10 series of FPGA parts, it would be immensely helpful.

Thank you sincerely for your assistance.

Warm regards,

Lou