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LouLoulou's avatar
LouLoulou
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1 year ago

Help: Cyclone 10CL025YE144 implementing LVDS receiver and what pins I can do this on and how>

Dear All, I hope this message finds you well. I am currently exploring the implementation of LVDS directly on an FPGA, particularly on a Cyclone 10 LP device. My aim is to interface it with an LVDS ...
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FvM's avatar
FvM
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1 year ago
Your device has maximal 18 LVDS pin pairs available, as listed in Cyclone 10 LP overview and device handbook. Probably not all IO banks of your design holding LVDS pins have 2.5V supply, thus the actual selection can be less.
LouLoulou's avatar
LouLoulou
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1 year ago
Sorry, I’m in idiot I replied to myself… i meant to do this here

Thank you for the information. Can you point me to a PDF file that explains the emulated LvDS pins versus the hard LVDS pins? I was under the impression that any open could be an emulated LVDS pair but I don’t think that’s the case. Can someone please help me understand this? I’ve been struggling to find relevant documentation.