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Vandana_GS's avatar
Vandana_GS
Icon for New Contributor rankNew Contributor
1 year ago

Hardware Implementation of Intel JESDIP Core with Agilex 7 and AFe7950EVM

Hi everyone,

I am trying to configure Intel JESDIP Core with Terasic Agilex SOM Module FPGA: Agilex AGFB014R24B2E2V development kit and TI's AFE7950EVM. While configuring the board in simplex mode(only transmit) we are getting error as follows in the system console.

Info : Master path=/devices/AGFB014R24A(.|R1|R2)|..@1#USB-1#Apollo Agilex/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_2/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_0/alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto.avalon_master and Index= 1

% start_basic_test
---Read Initial Status----
master_list_length = 2
PIO Status = 0x00000084
master_list_length = 2
Reset done!
master_list_length = 2
Enabled loopback done
master_list_length = 2
Waiting for reset seq active low...
Reset seq active low
Link and frame reset held
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Setting tx_test & rx_test registers...
Set test mode to PRBS test pattern
Waiting for reset seq active low...
Reset seq active low
Link and frame reset released
Waiting for reset seq active low...
Reset seq active low
master_list_length = 2
Error status registers cleared
TX Error Status= 0x00000084
RX Error0 Status= 0x00000084
RX Error1 Status= 0x00000002
master_list_length = 2
Pulse sysref done!
tx_status: 0x00000084
rx_status1: 0x00000084
rx_status2: 0x00000002
rx_status1_masked = 0x0
f_value: 1
k_value: 1
master_list_length = 2
Info : Master path=/devices/AGFB014R24A(.|R1|R2)|..@1#USB-1#Apollo Agilex/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_2/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_0/alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto.avalon_master
Status: 0x4 (Masked value)
Info: Bit 0 - Core PLL Locked
Info: Bit 1 - TX XCVR Ready
Info: Bit 2 - RX XCVR Ready
Info: Bit 3 - Patchk Data Error
Info: Bit 4 - Tx Link Error
Info: Bit 5 - Rx Link Error
TX Status0: 0x4 (Masked value)
Info: Bit 0 - SYNC_N
Info: Bit {2:1} - Data Link Layer (DLL)
- 00: Code Group Synchronization (CGS)
- 01: Initial Lane Alignment Sequence (ILAS)
- 10: User Data Mode
- 11: D21.5 test mode
RX Status0: 0x0 (Masked value)
Info: Bit 0 - SYNC_N
HW_TEST : FAIL
master_list_length = 2
Read Error Status Register
TX Error Status = 0x00000084
RX Error0 Status = 0x00000084
RX Error1 Status = 0x00000002

% read_status_pio
master_list_length = 2
PIO Status = 0x00000084

% reset
master_list_length = 2
Reset done!

% sloopback 0
master_list_length = 2
Disabled loopback done

% sysref
master_list_length = 2
Pulse sysref done!

% reset
master_list_length = 2
Reset done!

% sysref
master_list_length = 2
Pulse sysref done!

% read_status_pio
master_list_length = 2
PIO Status = 0x00000084
Could you please suggest what could be the problem because of which we are getting this error? The reference clock used is 184.32MHz and LMFS=12410 Data rate=7372.8Mbps.

When I am trying with TX-RX example design with same clock and LMFS configuration also I am getting the same error as shown above.

Thank you

Vandana G S

Configuration
Generic Io
Other Ips

5 Replies

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    Thanks for contacting Intel. I'm assigned to support request.

    I'll investigate on this case related and get back to you soon once I have any finding.

    Meanwhile can I check with you on:

    1. Quartus version
    2. OPN number
    3. Clock is stable? (have you checked it with CRO), since you are having issue with both example design as well as custom one.
    4. Check for any warnings while IP generation and timing issues.
    5. Have you checked with preset example design (since you mentioned that you have generated example design with your configurations).


    Thanks for your patience.

    Best regards,

    Harsh M


    • Vandana_GS's avatar
      Vandana_GS
      Icon for New Contributor rankNew Contributor
      1 year ago

      Hi,

      Thank you for the reply.

      1.The Quartus version we are using is 24.1.

      2.OPN number is AGFB014R24B2E2V.

      3. Please explain from which point on the FPGA can we check the clock stability.

      4. There were no warnings while IP generation and timing issues.

      5. I was able to generate the simulation with help of preset design with LMF=122 and Data rate=6144Mbps . But the same cannot be implemented in hardware as there is design restriction in the AFE7950 for data rate 6144Mbps. That is the reason to work with the reference clock used is 184.32MHz and LMFS=12410 Data rate=7372.8Mbps.

      Please assist us in resolving the issues.

      Thanks and regards,

      Vandana G S

  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    It seems you have no proper clock in your design.

    You can check using BTS(Board test system)

    Go to your Development Kit user guide, check under Board Test System section (example: 4.3. Control On-board Clock through Clock Controller GUI).

    Kindly download installer package for your device from intel (Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)) from there check DV kit user guide-> Board Test System section.


    You need to align the proper clock to the pin you have selected in design (Use schematic from the package to check for clock pins)


    Regards,

    Harsh M


  • Harshx's avatar
    Harshx
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    The links mentioned in the previous comment are for Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile) as an example, kindly check for your own development kit.