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Vandana_GS's avatar
Vandana_GS
Icon for New Contributor rankNew Contributor
1 year ago

Hardware Implementation of Intel JESDIP Core with Agilex 7 and AFe7950EVM

Hi everyone, I am trying to configure Intel JESDIP Core with Terasic Agilex SOM Module FPGA: Agilex AGFB014R24B2E2V development kit and TI's AFE7950EVM. While configuring the board in simplex mode(...
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Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case related and get back to you soon once I have any finding.

Meanwhile can I check with you on:

  1. Quartus version
  2. OPN number
  3. Clock is stable? (have you checked it with CRO), since you are having issue with both example design as well as custom one.
  4. Check for any warnings while IP generation and timing issues.
  5. Have you checked with preset example design (since you mentioned that you have generated example design with your configurations).


Thanks for your patience.

Best regards,

Harsh M


  • Vandana_GS's avatar
    Vandana_GS
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi,

    Thank you for the reply.

    1.The Quartus version we are using is 24.1.

    2.OPN number is AGFB014R24B2E2V.

    3. Please explain from which point on the FPGA can we check the clock stability.

    4. There were no warnings while IP generation and timing issues.

    5. I was able to generate the simulation with help of preset design with LMF=122 and Data rate=6144Mbps . But the same cannot be implemented in hardware as there is design restriction in the AFE7950 for data rate 6144Mbps. That is the reason to work with the reference clock used is 184.32MHz and LMFS=12410 Data rate=7372.8Mbps.

    Please assist us in resolving the issues.

    Thanks and regards,

    Vandana G S