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Vandana_GS
New Contributor
1 year agoHardware Implementation of Intel JESDIP Core with Agilex 7 and AFe7950EVM
Hi everyone, I am trying to configure Intel JESDIP Core with Terasic Agilex SOM Module FPGA: Agilex AGFB014R24B2E2V development kit and TI's AFE7950EVM. While configuring the board in simplex mode(...
Harshx
Occasional Contributor
1 year agoHi,
It seems you have no proper clock in your design.
You can check using BTS(Board test system)
Go to your Development Kit user guide, check under Board Test System section (example: 4.3. Control On-board Clock through Clock Controller GUI).
Kindly download installer package for your device from intel (Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)) from there check DV kit user guide-> Board Test System section.
You need to align the proper clock to the pin you have selected in design (Use schematic from the package to check for clock pins)
Regards,
Harsh M