Forum Discussion
sbj
New Contributor
New ContributorGTS Transceiver PLL Usage
From the GTS Transceiver PHY User Guide: “The GTS System PLL Clocks IP cannot be compiled or simulated as a standalone IP. It must always connect to the GTS PMA/FEC Direct PHY IP.” Does this restr...
sbjNew Contributor
New ContributorHi,
is there a way to find out which refclk should be applied to get a specific output clock on c1.
Usually the IP drop-down menu only shows a specific range.
Is there a way to influence that allowed range by tuning the refclk? If yes, any method/formula we use ?
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
User can only influence the IP by modifying the input reference clock value within datasheet specification. The tool then provides the output clock frequency options that it can offer.
May I know what are your input and output requirements?
Regards,
Altera Support
