New ContributorI'am using Stratix10 and Quartus Prime 19.1 software. Now I try to use PHY Lite IP. Reference clock to this IP comes from a PLL. And I got an error: "The permit_cal input port of IOPLL is not connected correctly". But PHY Lite IP does not have such input! How can I feed this IP by the PLL output?
Frequent Contributor
New ContributorHi RSree!
Thank you for answer. I understand it.
But PHY Lite IP has an internal PLL. And do not have permil_cal input. I can't connect the lock output from the upstream PLL to a PLL located inside the PHY Lite IP.
Frequent ContributorHi,
Basically the above error will caused due the below reason,
permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes. If it violates, the error will come out.
Please check the above kind of connection in your design if not can you please make a stand alone PHYLITE ip project and create the same error send me to further debugging
Frequent ContributorHi ,
I could not able to find the information from myside. Apology for the slow response.
Frequent ContributorHi ,
The Phylite IP have a dedicated PLL , which is supposed to get input from a dedciated input clock pin.
The PHY Lite for Parallel Interfaces IP core uses a reference clock that is sourced from
a dedicated clock pin to the PLL inside the IP core.
Reference Page no: 10
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf
Attaching the IP block diagram for your reference, it is clearly mentioned to connect to reference clock source.
Try to connect the input clock pin to phylite directly to input pin , the design you send is working correctly when connected to the dedicated input.
Frequent ContributorHi ,
Kindly let me know , you need further assistance
Frequent ContributorHi ,
If you do not have further query , kindly let me know can I close the thread
