Forum Discussion
AKorn9
New Contributor
New ContributorGreetings! How to add a "permit_cal" input to the PHY Lite IP?
I'am using Stratix10 and Quartus Prime 19.1 software. Now I try to use PHY Lite IP. Reference clock to this IP comes from a PLL. And I got an error: "The permit_cal input port of IOPLL is not connect...
Rahul_S_Intel1
Frequent Contributor
Frequent Contributor
AKorn9Hi RSree!
Thank you for answer. I understand it.
But PHY Lite IP has an internal PLL. And do not have permil_cal input. I can't connect the lock output from the upstream PLL to a PLL located inside the PHY Lite IP.
