Forum Discussion
AKorn9
New Contributor
New ContributorGreetings! How to add a "permit_cal" input to the PHY Lite IP?
I'am using Stratix10 and Quartus Prime 19.1 software. Now I try to use PHY Lite IP. Reference clock to this IP comes from a PLL. And I got an error: "The permit_cal input port of IOPLL is not connect...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
The Phylite IP have a dedicated PLL , which is supposed to get input from a dedciated input clock pin.
The PHY Lite for Parallel Interfaces IP core uses a reference clock that is sourced from
a dedicated clock pin to the PLL inside the IP core.
Reference Page no: 10
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf
Attaching the IP block diagram for your reference, it is clearly mentioned to connect to reference clock source.
Try to connect the input clock pin to phylite directly to input pin , the design you send is working correctly when connected to the dedicated input.
