Forum Discussion
AKorn9
New Contributor
New ContributorGreetings! How to add a "permit_cal" input to the PHY Lite IP?
I'am using Stratix10 and Quartus Prime 19.1 software. Now I try to use PHY Lite IP. Reference clock to this IP comes from a PLL. And I got an error: "The permit_cal input port of IOPLL is not connect...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
Basically the above error will caused due the below reason,
permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes. If it violates, the error will come out.
Please check the above kind of connection in your design if not can you please make a stand alone PHYLITE ip project and create the same error send me to further debugging
AKorn9New Contributor
New ContributorHi RSree!
I can't find permil_cal input in the PHY lite IP. You can find the simple testcase attached.
Thank you!
WBR, Alexander.
