Greetings! How to add a "permit_cal" input to the PHY Lite IP?

Hi,

Basically the above error will caused due the below reason,

permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes. If it violates, the error will come out.

Please check the above kind of connection in your design if not can you please make a stand alone PHYLITE ip project and create the same error send me to further debugging