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Thulasi's avatar
Thulasi
Icon for New Member rankNew Member
1 day ago

Global Clock & Regional clock inputs in Agilex M FPGA

Hi,

Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA.

  1. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ?
  2. Why multiple clock inputs of Global clocks and Regional clocks are  provided in F-Tile of Agilex M FPGA?
  3. Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? 
  4. When do we need to drive regional clock inputs ?
  5. When do I need to drive global clock inputs ?
  6. In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ?

 

Regards,

Thulasi 

 

 

Core Logic
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3 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    14 hours ago

    Hi,

    The F-tile transceiver channels are grouped in quads i.e. 4 channels in a group. Not all the reference clocks reach each of the FGT and FHT channel. You need not necessarily drive multiple reference clocks. Drive one of the global clocks that reach all the FGT channels i.e. either of Refclk 2, 3, 4 and 5 if all the channels you use can share the same frequency. Similarly FHT quad has its own refclk network.

    Kindly refer to the Reference Clock Network section of the F-tile Architecture user guide: 

    https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/reference-clock-network

     

    Regards

    • Thulasi's avatar
      Thulasi
      Icon for New Member rankNew Member
      13 hours ago

      Hi,

      Thanks for the response. 

      When two clocks of different values(390.625MHz & 156.25MHz at ref 2, 3) are required at the reference clock inputs of F-Tile ? It is observed in Agilex M/I based designs. 

      Regards

       

      • Ash_R_Intel's avatar
        Ash_R_Intel
        Icon for Regular Contributor rankRegular Contributor
        10 hours ago

        Hi,

        Are you referring to the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile)? If so, it is a generic dev kit. Clocks of different frequencies drive different reference clocks and there sources are also different. It just provides flexibility to the user to choose a clock as they need. 

         

        For example, tile 13A, refclk 4 (pin DJ14) is driven by CLK_390_625MHZ_2P, 390.625MHz clock. The source of it is SI5518 IC. At the same time the refclk 5 is driven by a 156.25MHz clock at pin DE14, source SI5394. Note that both SI5518 and SI5394 can also be modified to drive any other frequency using the clock controller tool.

         

        Depending on your application requirement you may choose either of the clock. 

        An example scenario could be: quad 2 channels require 390.625MHz refclk let's say, so you choose refclk 4. At the same time, quad 3 channels may require 156.25MHz refclk, so you choose refclk 5.

         

        Regards