Global Clock & Regional clock inputs in Agilex M FPGA

Hi,

Based on the F-tile architecture and the SyncE operation. 

1. Is SyncE clock recovery supported only on the FGT PMAs in Quad-2 and Quad-3?
Yes. The SyncE section says the recovered clock from the FGT PMA can be driven to dedicated clock output pins, and that each F-Tile has only two such outputs: FGT Quads 2 and 3. The architecture guide further says one RX CDR clock output must come from Quad 2 and the other from Quad 3.

2. Is it not possible to recover the SyncE clock from transceivers in Quad-0 and Quad-1?
Correct for the dedicated SyncE recovered-clock output path. Public docs say the “Enable dedicated CDR clock output” option is available only for Ports 8–15, which map to FGT Quads 2 and 3, not Quads 0 and 1.

3. Is SyncE clock recovery supported on FHT PMAs, or only FGT PMAs?
Based on the public F-Tile docs, it is only documented for FGT PMAs. The Ethernet SyncE chapter and the architecture chapter both describe FGT RX CDR clock output; the FHT clocking chapter describes FHT reference-clock inputs/common PLLs, not a corresponding SyncE recovered-clock output path.

4. Which F-Tile transceiver types and quads support SyncE clock recovery?

• Supported for SyncE recovered-clock output: FGT, Quad 2 and Quad 3 only.
• Not supported for that output path: FGT Quad 0/1 and FHT PMAs.

Refer: https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/fgt-and-system-pll-reference-clock-network

https://docs.altera.com/r/docs/683023/25.3.1/f-tile-ethernet-hard-ip-user-guide/clock-connections-in-synchronous-ethernet-operation

Regards