New Member
New MemberHi,
Thanks for the response.
When two clocks of different values(390.625MHz & 156.25MHz at ref 2, 3) are required at the reference clock inputs of F-Tile ? It is observed in Agilex M/I based designs.
Regards
Regular ContributorHi,
Are you referring to the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile)? If so, it is a generic dev kit. Clocks of different frequencies drive different reference clocks and there sources are also different. It just provides flexibility to the user to choose a clock as they need.
For example, tile 13A, refclk 4 (pin DJ14) is driven by CLK_390_625MHZ_2P, 390.625MHz clock. The source of it is SI5518 IC. At the same time the refclk 5 is driven by a 156.25MHz clock at pin DE14, source SI5394. Note that both SI5518 and SI5394 can also be modified to drive any other frequency using the clock controller tool.
Depending on your application requirement you may choose either of the clock.
An example scenario could be: quad 2 channels require 390.625MHz refclk let's say, so you choose refclk 4. At the same time, quad 3 channels may require 156.25MHz refclk, so you choose refclk 5.
Regards
