Generating normally distributed random numbers

For those interested in a synthesizable core for generating normally distributed random numbers (often used for additive white Gaussian noise - AWGN), we offer affordable IP cores for Altera FPGAs that generate normally distributed numbers accurate up to 7.2 standard deviations.

No,Thank you.

Did you have a question, or were you showing off your latest and greatest code?

TO_BE_DONE

Thanks for the replies.

I normally code as below

signal shift : std_logic_vector(15 downto 1);
process(reset,clk)
if reset = '1' then
    shift <= "010"&x"123";   -- seed
elsif rising_edge(clk) then
   if en = '1' then
     shift(1) <= shift(14) xor shift(15);  -- taps
     shift(2 to 15) <= shift(1 to 14);   -- shift
 
   end if;
end if;
end process;
 

Thats good to see. Im sure Ive seen someone from whoever the VHDL controlling body is coming up with something similar, that I think might make it into the next revision of VHDL (of course not synthesisable - only there for testbenching and verification.)

a nice looking VHDL package that can create a signal with a normal distribution:

absolutely, thanks for pointing out my oversight.