Forum Discussion
15 Replies
- Altera_Forum
Honored Contributor
you can use an LFSR. its easy to code looking at a diagram (try Wikipedia).
- Altera_Forum
Honored Contributor
--- Quote Start --- you can use an LFSR. its easy to code looking at a diagram (try Wikipedia). --- Quote End --- But can you make these easily Normally distributed (ie. bell curve with high probability around the centre of the range)? - Altera_Forum
Honored Contributor
If you are interested in LFSR automatic generated code, you could try this link to have a look :
http://www.jnicolle.com/?page=lfsr - Altera_Forum
Honored Contributor
Tricky: good point, i was thinking of pseudo-white noise as having a normal distribution, though i haven't checked.
- Altera_Forum
Honored Contributor
--- Quote Start --- Tricky: good point, i was thinking of pseudo-white noise as having a normal distribution, though i haven't checked. --- Quote End --- a standard pseudo random number generator would have a flat distribution, with every number only appearing once in the sequence. You can try an make it appear more random by having more bits than you actually use, but after the entire sequence, every value appears the same number of times. - Altera_Forum
Honored Contributor
absolutely, thanks for pointing out my oversight.
this is going to bother me all day. :) - Altera_Forum
Honored Contributor
--- Quote Start --- It is often incorrectly assumed that Gaussian noise (i.e., noise with a Gaussian amplitude distribution — see normal distribution) is necessarily white noise, yet neither property implies the other. Gaussianity refers to the probability distribution with respect to the value i.e. the probability that the signal has a certain given value, while the term 'white' refers to the way the signal power is distributed over time or among frequencies. --- Quote End --- :o http://en.wikipedia.org/wiki/white_noise - Altera_Forum
Honored Contributor
a nice looking VHDL package that can create a signal with a normal distribution:
http://read.pudn.com/downloads111/sourcecode/asm/459855/random1.vhd__.htm - Altera_Forum
Honored Contributor
Thats good to see. Im sure Ive seen someone from whoever the VHDL controlling body is coming up with something similar, that I think might make it into the next revision of VHDL (of course not synthesisable - only there for testbenching and verification.)
- Altera_Forum
Honored Contributor
I normally code as below
signal shift : std_logic_vector(15 downto 1); process(reset,clk) if reset = '1' then shift <= "010"&x"123"; -- seed elsif rising_edge(clk) then if en = '1' then shift(1) <= shift(14) xor shift(15); -- taps shift(2 to 15) <= shift(1 to 14); -- shift end if; end if; end process;