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Altera_Forum's avatar
Altera_Forum
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15 years ago

Generating normally distributed random numbers

Hi, Does anyone have any tips regarding how to generate normally distributed pseudo-random numbers in Verilog or VHDL? Any help would be most appreciated. Regards
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I normally code as below 


signal shift : std_logic_vector(15 downto 1);
process(reset,clk)
if reset = '1' then
    shift <= "010"&x"123";   -- seed
elsif rising_edge(clk) then
   if en = '1' then
     shift(1) <= shift(14) xor shift(15);  -- taps
     shift(2 to 15) <= shift(1 to 14);   -- shift
 
   end if;
end if;
end process;