Altera_ForumHonored Contributor15 years agoGenerating normally distributed random numbers Hi, Does anyone have any tips regarding how to generate normally distributed pseudo-random numbers in Verilog or VHDL? Any help would be most appreciated. Regards
Altera_ForumHonored Contributor15 years agoabsolutely, thanks for pointing out my oversight. this is going to bother me all day. :)
Recent DiscussionsJTAG Chain Broken on Agilex 7-I Dev KitCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationRequest for Cyclone V Pinout File Information