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Altera_Forum
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Honored ContributorGenerating a signal with noise
What i am doing is i am trying to do is add random numbers to a signal to find PSD later. I wrote a code for random numbers generator which is working fine shown below:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY random IS ------> Interface GENERIC (n : INTEGER := 32); -- Input bit width PORT( clk : IN STD_LOGIC; random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END random; ARCHITECTURE Behavioral of random is BEGIN PROCESS(clk) VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0) := (n-1 => '1' , OTHERS => '0'); VARIABLE temp : STD_LOGIC := '0'; BEGIN IF(RISING_EDGE(clk)) THEN temp := rand_temp(n-1) XOR rand_temp(n-2); rand_temp(n-1 DOWNTO 1) := rand_temp(n-2 DOWNTO 0); rand_temp(0) := temp; END IF; random_num <= rand_temp; END PROCESS; END; After that i tried to add the random signal to a known signal to get a new signal so i can find PSD. I wrote a code for that and i am getting some errors. The code is PACKAGE n_bit_int IS-- User-defined type SUBTYPE BITS32 IS INTEGER RANGE -2**32 TO 2**32-1; -- -256 ~255 SUBTYPE BITS33 IS INTEGER RANGE -2**33 TO 2**33-1; -- -512 ~511 END PACKAGE n_bit_int; LIBRARY WORK; USE WORK.n_bit_int.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.MATH_REAL.ALL; ENTITY cumulants IS GENERIC (n : INTEGER := 32); PORT( clk : IN STD_LOGIC; x0 : IN BITS32; x1 : IN BITS32; x2 : IN BITS32; x3 : IN BITS32; y0 : OUT BITS33; y1 : OUT BITS33; y2 : OUT BITS33; y3 : OUT BITS33 ); END ENTITY cumulants; ARCHITECTURE Behavioral of cumulants is COMPONENT random PORT( clk : IN STD_LOGIC; random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END COMPONENT random; BEGIN PROCESS VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0); BEGIN u1 : PORT MAP ( clk => clk1, random => rand_temp ); y0 <= x0 + rand_temp; y1 <= x1 + rand_temp; y2 <= x2 + rand_temp; y3 <= x3 + rand_temp; END PROCESS; END; The errors are Error (10500): VHDL syntax error at cumulants.vhd(49) near text "PORT"; expecting "(", or an identifier ("port" is a reserved keyword), or a sequential statement Error (10500): VHDL syntax error at cumulants.vhd(49) near text ";"; expecting ":=", or "<=" Please help me. Where am i going wrong.22 Replies
Altera_Forumtry this:
u1 : random PORT MAP ( clk => clk1, random => rand_temp ); you forgot the random before the port map. Is this just for testbench code? VHDL already has a built in random number generator for testbenches.- Altera_Forum
If you need a random number generator that you can synthesize, then look at this tutorial and code:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip In the code you have above, it looks like you are using a linear feedback shift register (LFSR) to generate your random noise. An LFSR is used to generate a pseudo-random binary sequence (PRBS), but its only one bit of the LFSR that actually has a random characteristic (that is why PRBS has binary in the name). In the code above, you are using the full LFSR register contents, and these are not random. The tutorial shows how you can create a multi-bit output LFSR/PRBS generator (and provides VHDL code to do so). Cheers, Dave - Altera_Forum
additionally, the cookbook (http://www.altera.com/literature/manual/stx_cookbook.pdf) demonstrates a way to use a ring oscillator to generate randomness
- Altera_Forum
Thanks for that man..
- Altera_Forum
How that was very help full dave..Thanks
- Altera_Forum
Guys i corrected my mistake and here is the code
PACKAGE n_bit_int IS-- User-defined type SUBTYPE BITS32 IS INTEGER RANGE -2**32 TO 2**32-1; -- -256 ~255 SUBTYPE BITS33 IS INTEGER RANGE -2**33 TO 2**33-1; -- -512 ~511 END PACKAGE n_bit_int; LIBRARY WORK; USE WORK.n_bit_int.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.MATH_REAL.ALL; ENTITY cumulants IS GENERIC (n : INTEGER := 32); PORT( clk : IN STD_LOGIC; x0 : IN BITS32; x1 : IN BITS32; x2 : IN BITS32; x3 : IN BITS32; y0 : OUT BITS33; y1 : OUT BITS33; y2 : OUT BITS33; y3 : OUT BITS33 ); END ENTITY cumulants; ARCHITECTURE Behavioral of cumulants is COMPONENT random PORT( clk : IN STD_LOGIC; random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END COMPONENT random; BEGIN PROCESS VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0); BEGIN u1 : random PORT MAP ( clk => clk, random_num => rand_temp ); y0 <= x0 + rand_temp; y1 <= x1 + rand_temp; y2 <= x2 + rand_temp; y3 <= x3 + rand_temp; END PROCESS; END; Now i am getting a new errors Error (10500): VHDL syntax error at cumulants.vhd(49) near text "PORT"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at cumulants.vhd(49) near text ";"; expecting ":=", or "<=" Is there anything i am missing because i don't think i am. - Altera_Forum
Move u1 out of the process.
Cheers, Dave - Altera_Forum
Hi dave thanks for the reply
PACKAGE n_bit_int IS-- User-defined type SUBTYPE BITS32 IS INTEGER RANGE -2**32 TO 2**32-1; -- -256 ~255 SUBTYPE BITS33 IS INTEGER RANGE -2**33 TO 2**33-1; -- -512 ~511 END PACKAGE n_bit_int; LIBRARY WORK; USE WORK.n_bit_int.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY cumulants IS GENERIC (n : INTEGER := 32); PORT( clk : IN STD_LOGIC; x0 : IN BITS32; x1 : IN BITS32; x2 : IN BITS32; x3 : IN BITS32; y0 : OUT BITS33; y1 : OUT BITS33; y2 : OUT BITS33; y3 : OUT BITS33 ); END ENTITY cumulants; ARCHITECTURE Behavioral of cumulants is COMPONENT random PORT( clk : IN STD_LOGIC; random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END COMPONENT random; VARIABLE rand_temp : STD_LOGIC_VECTOR(n-1 DOWNTO 0); SIGNAL s : INTEGER; BEGIN u1 : random PORT MAP ( clk => clk, random_num => rand_temp ); PROCESS BEGIN s <= CONV_INTEGER(rand_temp); y0 <= x0 + s; y1 <= x1 + s; y2 <= x2 + s; y3 <= x3 + s; END PROCESS; END; I am getting an error as Error (10482): VHDL error at cumulants.vhd(49): object "CONV_INTEGER" is used but not declared is my deceleration of conversation bad? can you suggest me how i can improve my vhdl skills?? --:) ADI - Altera_Forum
You need to find yourself a good VHDL book.
Your code does not need the keywords 'PROCESS', 'BEGIN', 'END PROCESS', since you have not created any code that needs to go in the process. For type conversion, you need to look at what the numeric_std library provides. Hint: to_integer, but it takes an unsigned, so you need to figure out how a std_logic_vector gets converted to unsigned, and then convert unsigned to integer. Your code will look like s <= to_integer(<something here>(rand_temp)); I don't want to spoil your chance to learn by giving you all the details, so please search around and try to figure it out. Cheers, Dave - Altera_Forum
Hi dave
Thanks for the advice. I worked on the code and the output i am expecting is sum on input and random noise but i am getting what ever input i give as output. Here is the code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY cumulants IS GENERIC (n : INTEGER := 32); PORT( clk : IN STD_LOGIC; x : IN STD_LOGIC_VECTOR (n-1 DOWNTO 0); y : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END ENTITY cumulants; ARCHITECTURE Behavioral of cumulants is COMPONENT random PORT( clk : IN STD_LOGIC; random_num : OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0) ); END COMPONENT random; SHARED VARIABLE rand_temp1 : STD_LOGIC_VECTOR(n-1 DOWNTO 0); SIGNAL s : INTEGER; BEGIN u1 : random PORT MAP ( clk => clk, random_num => rand_temp1 ); PROCESS(clk) BEGIN IF(RISING_EDGE(clk)) THEN y <= x OR rand_temp1 ; END IF; END PROCESS; END; The code for random number is shown above any help would be appreciated Aditya
