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Altera_Forum
Honored Contributor
13 years agoGenerating a signal with noise
What i am doing is i am trying to do is add random numbers to a signal to find PSD later. I wrote a code for random numbers generator which is working fine shown below: LIBRARY ieee; USE ie...
Altera_Forum
Honored Contributor
13 years agotry this:
u1 : random PORT MAP ( clk => clk1, random => rand_temp ); you forgot the random before the port map. Is this just for testbench code? VHDL already has a built in random number generator for testbenches.